1. Field of the Invention
The present invention relates to a method of fabricating a multi-layered wiring suitable for manufacturing LSI or other devices, and more particularly to a method of fabricating multi-layered wiring which is highly resistant to stress migration.
2. Description of the Related Art
Such a conventional method of fabricating multi-layered wiring is known in that an interlayer insulating layer is made by a lamination of the first silicon oxide layer formed by plasma-enhanced chemical vapor deposition (PECVD), the second silicon oxide layer is formed on the first silicon oxide layer using hydrogen silsesquioxane resin and the third silicon oxide layer is formed on the second silicon oxide layer by PECVD (for example, refer to JP-A 7-240460).
According to an investigation by the present inventors, it was found that there is a problem that the resistance to stress migration is low if a multi-layered wiring structure is fabricated by the use of an interlayer insulating layer made by a lamination of the first to third silicon oxide films as mentioned above.
FIG. 10 shows a multi-layered wiring structure having such an interlayer insulating layer, the structure of which can be obtained as follows: a borophosphosilicate glass (BPSG) film 14 is formed by CVD on a silicon oxide layer 12 covering a surface of the semiconductor substrate 10 made of silicon. Thereafter, wiring layers 16A and 16B are formed on the BPSG film 14 by sputtering, reflowing and patterning an aluminium (Al) alloy layer.
On the BPSG film 14, a conformal silicon oxide layer 18 is formed by PECVD, covering the wiring layers 16A and 16B. On the silicon oxide layer 18, a planarized silicon oxide layer 20 is formed by spin coating of a solution of hydrogen silsesquioxane resin and by subsequent heat treatment. On the silicon oxide layer 20, a silicon oxide layer 22 is formed by PECVD. The silicon oxide layer 22 has a flat surface because it is formed on a flattened surface.
A connecting hole 24 is formed through the interlayer insulating layer made by a lamination of the silicon oxide layers 18, 20 and 22 by partly an isotropic wet etching using, resist layer as a mask to have a reduced step height and partly an anisotropic dry etching. On the silicon oxide layer 22, a wiring layer 26 is formed to be electrically connected to the wiring layer 16 via the connecting hole 24, by sputtering, reflowing and patterning an Al alloy layer.
After an annealing in hydrogen atmosphere for reducing process damages, a passivation film 28 made of silicon nitride is formed covering the wiring layer 26 on the silicon oxide layer 22 by PECVD.
As the result of a stress migration test in which the above-mentioned multi-layered wiring structure is heated at 200.degree. C. for 2000 hours, it was found that a void V is generated, resulting in an increase of the wiring resistance or a break-down.